The interconnection architecture in the system has been widely used. Physical constraints such as chip boundaries and circuit board edges require the system to be partitioned. The I / O standards such as GPIB or USB, and the internally interconnected microprocessor bus define interconnection methods. In addition to these standards, connections are often used in asynchronous and point-to-point applications.
Today, however, the rapid growth of bandwidth between subsystems, the risk of low-latency paths expanding at the boundaries of subsystems, and strict power consumption and cost budgets have made everything more complicated. In many designs, it is impossible to fill the CPU bus or peripheral bus in the system. For subsystems implemented in a system on chip (SoC), some chip designers can use these subsystems to understand your system interconnection architecture in advance. Due to the low I / O voltage and extremely short rise time, point-to-point interconnection encounters significant timing, signal integrity, and circuit board design challenges.
For this increasingly complex situation, other solutions are needed. High-speed serial interconnection has been mainly used in the communications industry to transmit data streams over long distances. Using advanced silicon process technology, in many systems, the interface of these serial links becomes very small, and the data rate is high enough, multi-gigabit serial links have replaced parallel buses and even asynchronous I / O.
An obvious example is PCI Express (PCIe). The original PCI was a very traditional parallel synchronous bus. As the bandwidth requirements of personal computers have grown, Intel has migrated this topology to multiple paths on high-speed serial links. Similar developments have also appeared in mass storage devices, and the old AT connection bus has become the very familiar Serial ATA (SATA).
The application of these concepts has exceeded the peripheral bus. In order to understand why high-speed serial links can be applied to point-to-point connections or even on a single board boundary, let us understand some system partitioning issues.
System division
In an ideal theoretical system structure, the system division is based entirely on system processes based on data and control flow graphs. You draw the diagram, and then divide the functional modules into subsystems, and the subsystems are divided into larger groups, which reduces the bandwidth requirements and increases the delay constraints of the links between the subsystems. Then, you can implement each connection between subsystems with the shortest suitable interconnection according to the needs of this link.
This method is very suitable for blank circuit boards. This is actually very similar to the early stages of SoC design and FPGA use. However, most designs today start with commercial chips: dedicated standard products (ASSP) or microcontroller units (MCU). These SoCs put forward a lot of division requirements for us, as shown in Figure 1. The chip we choose determines the boundaries of our subsystems and which interconnect technology should be used. If the only external interconnection of your MCU is the AMBA APB peripheral bus, or DDR2 memory bus, and some general-purpose I / O pins, then this is your choice.
Figure 1. The chips on the motor control circuit board are grouped by subsystem.
Even so, partitioning is still an important step in system design. Moreover, you must compare the assumptions made by SoC designers with the actual physical boundaries of the system, bandwidth requirements, and latency requirements. Therefore, you need to identify the subsystem: put together chips that need to exchange large amounts of data, such as SoC and DRAM. You can put the narrowband between them and the chips that do not have high requirements on delay in different subsystems, such as MCU and system monitoring analog-to-digital converter (ADC). After including all the functional modules in the system through this grouping method, you can turn to characterizing the links between the subsystems.
Feature description
In an SoC-based system, characterizing the interconnection between subsystems does not seem to make much sense. The SoC's I / O options define the interface very well. But as a system designer, you still need to answer some important questions, and there are still some options that may not be clear.
The problem is divided into bandwidth, delay and cost. Bandwidth is the foundation of these problems. If your suggested interconnection scheme is feasible, then you should clearly know the bandwidth requirements of each subsystem. Generally speaking, this is actually a question of little significance. SoC designers design the pathways to be very long to ensure that the I / O on the chip is much greater than the predicted task requirements. There is usually enough DRAM bandwidth to handle all instructions and data streams generated by the chip's CPU cache. Usually high-speed buses such as PCIe connect to the main system or broadband peripherals and accelerators. Moreover, there is a dedicated I / O interface compatible with the standard.
But what if the SoC designer did not foresee the work you did? Sometimes, based on your analysis of the system architecture, the SoC you choose fully meets your interface requirements. In other cases, you may find that in some places you will encounter bottlenecks, and in some cases you will encounter unused bandwidth, or interfaces that are not used at all. In all these cases, you may rethink the purpose of these interfaces. Or, if you build an SoC by pooling intellectual property (IP) in the FPGA, you can rearrange the system interconnection architecture more flexibly. In particular, you should carefully handle the most demanding data streams in the system. It's not a good idea to dump everything onto a shared bus automatically, even a PCIe bus.
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