A Design of Bandgap Reference Voltage Source Based on LDO Regulator Jin Ruicai, Dai Qingyuan, Huang Wenli, Institute of Micro-Nano Science and Technology, Shanghai Jiaotong University, National Key of Micro/Nano Processing Technology. This circuit uses a triode as the input to the op amp while eliminating the need for redundant equivalent diodes. This not only simplifies the structure, but also consumes less power. QuQ2, M5, and M6 form an operational amplifier with high power and high power supply rejection ratio. The dish 1, the dish 3, the dish 4, and the dish 7 are bias tubes, and the capacitor 匚 is used for the frequency compensation of the operational amplifier, and the phase margin of the operational amplifier is added to prevent the Vref oscillation output. At the same time, the current through Q3, R3 produces a current proportional to absolute temperature (PTAT) / 3. ENH in the circuit as the enable terminal, when the high level turns off the bandgap reference source.
Since Vbe3 has a negative temperature coefficient and Vt has a positive temperature coefficient, as long as the appropriate R2, R3 and n are selected, a temperature-independent reference voltage 1111 can be obtained to reduce the offset voltage, and R2 takes 6kAR3 to take 47%.
In order to overcome the drift of the process, the middle R3 is composed of a resistor network with adjustable resistance. As shown. R3 consists of a large resistor Rd connected in series with three small resistors Rn, 2Rn and 4Rn1121. 3LDO buffer circuit structure design and analysis combines the bandgap reference described above with the LDO buffer, as shown. M1~M6 form a two-stage operational amplifier. Here, Vdd is obtained from the input voltage Vcc and the reference voltage Vref. Since Vref is around 1.28V, the common mode input voltage of the error op amp is required to be around 1.28V, and the PMOS tube is selected as the input pair.
By adjusting, /b2R2 = today R1, so it can be seen from the above equation that G is proportional to Rl. When Rl is small, G is also small. In order to ensure a certain negative feedback loop gain, the error is finally required to obtain a higher margin, so a two-stage operational amplification VREF=VBE3+/3R3+(/3+//)R2 is selected. At the same time, in order to ensure sufficient phase margin, G is a Miller/b2R2(2) capacitor, and a negative feedback loop main pole is formed on the left side of C1.
Because for the buffer, in order to achieve a large load current on M7, drive a small load resistor Rl, when Rl is to achieve a small offset voltage of the error op amp, in the circuit diagram and layout design, the area of ​​the big Mi, M2 And the area of ​​M3, M4. At the same time, in the layout layout, pay attention to the symmetric arrangement of Ml, M2 and M3, M4.
The negative feedback loop equalizes the two input potentials of the op amp so that the current flowing through the resistor is constant, so the output Vdd is constant. Then, Vdd can provide power supply to other modules in the power chip, such as digital control module, PWM comparator circuit, oscillator circuit and other protection circuits.
4 The simulation result is the curve of the output voltage with temperature when the power supply voltage is 5V. It can be seen from the figure that when the temperature changes between 40C and 125C, the Vref variation range is within 5 4mV, also when the power supply voltage is 12V. The Vref variation range is also within 55mV, which is equivalent to 25ppm (.e.25X106).
When the low frequency is displayed, the power supply rejection ratio is 138dB. It can be seen that the output voltage changes only when the power supply voltage changes between 4V and 12V. The bandgap reference circuit designed in this paper is combined with the LD0 buffer. The simulation results are shown in the figure. .
As shown, the minimum load resistance is approximately 650.
The maximum load current is approximately 55 mA. This indicates that the design achieves a strong load capacity of the LDO.
As shown by 0, when the load resistance is 1KQ, when the load capacitance is 10pF, the buffer negative feedback loop gain is 29dB. The phase margin is 633.
1 is the linear adjustment rate of the circuit. As can be seen from the figure, in the process of temperature change of 27C, when V. changes from 4V to 12V, the output voltage only changes by about 17mV. The output is always stable at around 3.3V, which meets the requirements.
5 Conclusion This paper presents a design of a bandgap reference based on LDO regulator. In the trend that the LDO chip is getting smaller and smaller, a simplified bandgap reference voltage source using the three-stage tube as the op amp input is designed. Compared to traditional bandgap references, high performance is achieved while simplifying the design. The reference voltage source also has high power supply rejection ratio and good temperature characteristics. The simulation results of Hua Hong NEC (HHNEC) Q 35MmBCD process show that the bandgap reference voltage of 25Xl-VC temperature coefficient is generated under the 5V power supply. In terms of LDO buffers, the traditional structure is adopted. The simulation results show that multiple indicators meet the requirements.
Since Vbe3 has a negative temperature coefficient and Vt has a positive temperature coefficient, as long as the appropriate R2, R3 and n are selected, a temperature-independent reference voltage 1111 can be obtained to reduce the offset voltage, and R2 takes 6kAR3 to take 47%.
In order to overcome the drift of the process, the middle R3 is composed of a resistor network with adjustable resistance. As shown. R3 consists of a large resistor Rd connected in series with three small resistors Rn, 2Rn and 4Rn1121. 3LDO buffer circuit structure design and analysis combines the bandgap reference described above with the LDO buffer, as shown. M1~M6 form a two-stage operational amplifier. Here, Vdd is obtained from the input voltage Vcc and the reference voltage Vref. Since Vref is around 1.28V, the common mode input voltage of the error op amp is required to be around 1.28V, and the PMOS tube is selected as the input pair.
By adjusting, /b2R2 = today R1, so it can be seen from the above equation that G is proportional to Rl. When Rl is small, G is also small. In order to ensure a certain negative feedback loop gain, the error is finally required to obtain a higher margin, so a two-stage operational amplification VREF=VBE3+/3R3+(/3+//)R2 is selected. At the same time, in order to ensure sufficient phase margin, G is a Miller/b2R2(2) capacitor, and a negative feedback loop main pole is formed on the left side of C1.
Because for the buffer, in order to achieve a large load current on M7, drive a small load resistor Rl, when Rl is to achieve a small offset voltage of the error op amp, in the circuit diagram and layout design, the area of ​​the big Mi, M2 And the area of ​​M3, M4. At the same time, in the layout layout, pay attention to the symmetric arrangement of Ml, M2 and M3, M4.
The negative feedback loop equalizes the two input potentials of the op amp so that the current flowing through the resistor is constant, so the output Vdd is constant. Then, Vdd can provide power supply to other modules in the power chip, such as digital control module, PWM comparator circuit, oscillator circuit and other protection circuits.
4 The simulation result is the curve of the output voltage with temperature when the power supply voltage is 5V. It can be seen from the figure that when the temperature changes between 40C and 125C, the Vref variation range is within 5 4mV, also when the power supply voltage is 12V. The Vref variation range is also within 55mV, which is equivalent to 25ppm (.e.25X106).
When the low frequency is displayed, the power supply rejection ratio is 138dB. It can be seen that the output voltage changes only when the power supply voltage changes between 4V and 12V. The bandgap reference circuit designed in this paper is combined with the LD0 buffer. The simulation results are shown in the figure. .
As shown, the minimum load resistance is approximately 650.
The maximum load current is approximately 55 mA. This indicates that the design achieves a strong load capacity of the LDO.
As shown by 0, when the load resistance is 1KQ, when the load capacitance is 10pF, the buffer negative feedback loop gain is 29dB. The phase margin is 633.
1 is the linear adjustment rate of the circuit. As can be seen from the figure, in the process of temperature change of 27C, when V. changes from 4V to 12V, the output voltage only changes by about 17mV. The output is always stable at around 3.3V, which meets the requirements.
5 Conclusion This paper presents a design of a bandgap reference based on LDO regulator. In the trend that the LDO chip is getting smaller and smaller, a simplified bandgap reference voltage source using the three-stage tube as the op amp input is designed. Compared to traditional bandgap references, high performance is achieved while simplifying the design. The reference voltage source also has high power supply rejection ratio and good temperature characteristics. The simulation results of Hua Hong NEC (HHNEC) Q 35MmBCD process show that the bandgap reference voltage of 25Xl-VC temperature coefficient is generated under the 5V power supply. In terms of LDO buffers, the traditional structure is adopted. The simulation results show that multiple indicators meet the requirements.
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