From the results of recent work and study, I have summarized the following methods for timing constraints. The order from easy to difficult is as follows:
This is the most basic, so the label is 0.
2. Core frequency constraint + timing exception constraintTiming exception constraints include FalsePath, MulticyclePath, MaxDelay, MinDelay. But this is not the most complete timing constraint. If there are only these constraints, it means that the designer's thinking is still limited to the FPGA chip.
3. Core frequency constraint + timing exception constraint + I/O constraintI/O constraints include pin assignment location, idle pin drive mode, external wiring delay (InputDelay, OutputDelay), pull-up and pull-down resistance, drive current intensity, etc. The timing constraint after adding the I/O constraint is the complete timing constraint. As a device on the PCB, FPGA is a part of the timing closure of the entire PCB system. FPGA, as a part of PCB design, requires PCB design engineers to read and analyze its I/O TIming Diagram like all COTS devices. FPGA is different from COTS devices in that its I/O TIming can be adjusted within a certain range in the later stage of the design; nevertheless, it is best to give full consideration in the early stage of PCB design and include it in the design document. riple
It is precisely because the FPGA I/O TIming will change during the design period, it is an important factor to ensure that the design is stable and controllable to constrain it accurately. After the FPGA is recompiled, the unstable operation of the FPGA to the external device may be caused by this.
4. Core frequency constraint + timing exception constraint + I/O constraint + Post-fit NetlistThe process of introducing Post-fit Netlist is to start with a successful timing closure result, and fix the placement position and routing result (Netlist) of a specific set of logic (Design ParTItion) implemented on the FPGA to ensure that the placement and routing result can be Reproduced in the new compilation, correspondingly, the timing closure result of this group of logic is guaranteed. This part of the process of retaining the results of the last compilation is Incremental Compilation. The type of the retained netlist and the degree of retention can be set, not only the Post-fit Netlist, so as to obtain the corresponding retention strength and optimization effect. Thanks to the strong support of EDA tools, although it is a fine-grained constraint that is accurate to the gate level, the designer only needs to perform a series of setting operations, and does not need to care about the specific information of the layout and wiring. Because there are too many constraints that are accurate to the gate level, they cannot be saved in the qsf file. The retained netlist can be output to a separate file qxp in the form of Partial Netlist, which is added together with the rough configuration information in the qsf file. The amount of compilation.
5. Core frequency constraint + timing exception constraint + I/O constraint + LogicLockLogicLock is a layout constraint performed at the bottom of the FPGA device. The constraints of LogicLock are coarse-grained, and only specify the layout position and size (LogicLock Regions) that can be adjusted for the top-level module or sub-module of the design. A successful LogicLock requires the designer to predict the possible timing closure goals, consider the impact of specific logic resources (pins, memory, DSP) and the location of the LogicLock Region on the timing, and can refer to the results of the previous timing closure. The process of weighing and planning the physical layout of the FPGA bottom layer is FloorPlanning. LogicLock gives designers more control over the location and scope of the layout, and can effectively convey the designer's design intent to the EDA tool, avoiding the EDA tool from blindly optimizing non-critical paths due to the lack of layout priority information. Since the layout position change of the module in each compilation is limited to the optimal fixed range, the reproducibility of the timing closure result is also higher. Due to its coarse-grained nature, the constraint information of LogicLock is not much and can be retained in the qsf file.
It should be noted that methods 3 and 4 can often be mixed, that is, for the LogicLock Region specified by FloorPlanning, use it as a Design Partition for Incremental Compilation. This is the reason why the above two methods are easy to confuse.
6. Core frequency constraint + timing exception constraint + I/O constraint + register layout constraintRegister layout constraints are fine-grained layout constraints that are accurate to the register or LE level. The designer obtains reliable timing closure results by applying precise control to the design. It is a huge project to manually constrain the layout of each register in the design and ensure timing closure, which indicates that the designer can fully control the physical realization of the design. This is an ideal goal, and it cannot be accomplished in a limited time. The usual approach is that the designer imposes register placement constraints on parts of the design and obtains timing closure information by actually running the placement and routing tools, and approaching the expected timing goal through several iterations. riple
Not long ago, I saw a design like this: each register of a sub-module is given a specific layout location constraint. The timing closure of the module is correspondingly guaranteed during each recompilation process. After analysis, the design and constraints of this sub-module were initially carried out in the schematic diagram. After the timing closure goal was reached, the design was converted to HDL language description, and the corresponding constraints were also saved in the configuration file.
7. Core frequency constraint + timing exception constraint + I/O constraint + specific path delay constraintGood timing constraints should be "guided" rather than "mandatory". By giving the timing delay range of the critical path in the design, the specific and subtle work is left to the EDA tool to realize freely within the limited range of this constraint. This is also an ideal goal. It requires the designer to know every timing path. The designer needs to distinguish which paths can be converged by core frequency and simple timing exception constraints, and which paths must be MaxDelay and MinDelay. Yes, one cannot be left out, and it also needs the strong support of EDA tools "understanding". Setting the path delay constraint is indirectly setting the layout constraint, but it is more flexible than the above-mentioned methods 3, 4, and 5, and its accuracy is not lost. The essence of timing constraints is to achieve timing closure through timing constraints rather than explicit layout and netlist constraints.
I remember some netizens said that "good timing is designed, not constrained." I have always used this sentence as a guide for my own logic design and timing constraints. Good constraints must be premised on good design. Without a good design, no amount of effort is made to constrain. However, the quality of the design can also be checked through the correct constraints, and the timing analysis report can be used to check out the imperfect timing of the design and modify it. The goal of perfecting the design can also be achieved through several iterations of "analysis-modification-analysis". It should be said that design is the foundation of constraints, and constraints are the guarantee of design. The two are in a complementary relationship.
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