OFweek Electronic Engineering Newsletter provides simpler, faster, and lower power hardware with a free, open, and simple instruction set architecture. This sounds good enough, and it is even more pleasing that RISC-V is currently advancing this work. RISC-V is an instruction set architecture (ISA) developed by engineers at the University of California, Berkeley and is now managed by a foundation.
People already know that, as Moore's Law no longer provides efficient returns as it has in the past, it means that an independent general-purpose processor is no longer the "hot spot" of innovation.
Ted Speers, senior technical director of product architecture and planning at Microsemi's SoC business unit, and a board member of the RISC-V Foundation, said: "We shouldn't spend so much money on processors and the cost of processors should drop. You innovate from accelerators and new architectures."
Drew Wingard, chief technology officer of Sonics, pointed out: "Technically, the ability to manage complexity has been extended to 32-bit RISC microprocessors, and this is no longer seen as a complex object of processing."
Drew Wingard said: “The entry barrier for microprocessor instruction set architecture is software and ecosystem. Overall, there is nothing magical about the basic technology of microprocessors. RISC-V essentially takes it to the next level of logic. Let's try to capture an instruction set architecture and enough structure and automation so that we can build the processor family more easily. We will choose to distribute it as an open source IP so that the community can add in. With the open-source movement side, it also has a configurable processor movement side, and it has the opportunity to give us a fresh look at the cost of microprocessor IP."
The commercial terminal in this market is likely to be the same as Linux, with vendors adding their own IP and technical support. Now, RISC-V core suppliers include Nvidia, Andes Technology, Cortus and Codasip.
Rocket cores based on RISC-V map to ZedBoard running Linux. (Source: HotChips)
Currently, the mainstream ISAs in the community are x86, ARM, ARC, MIPS, and PowerPC, as well as other ISAs used in GPUs and DSPs. However, RISC-V turned out to have made some progress. Nvidia announced that its SoC will include RISC-V control processors. The soft-core supplier Andes Technology also uses RISC-V's 64-bit architecture.
Anush Mohandass, vice president of marketing and business development at NetSpeed ​​Systems, said that from an architectural point of view, RISC-V is simple and elegant, but the success of the processor is more important than the processor itself.
Mohandass said: “The key issue is the software ecosystem. How will they develop? This is a chicken-and-egg problem. Developers are more than design, and some people must start the process. This is where Intel dominates the data center. And why ARM dominates the mobile space. Yes, part of it is architecture, but part of it is the ecosystem. Once it is motivated, it must be broken with new architecture. RISC-V will be in the emerging Internet of Things. The area is hedging because there is not a large unified platform there. RISC-V will have an opportunity there."
Those who support the RISC-V platform agree with this view. Professor UC Berkeley, chairman of the RISC-V Foundation and co-founder of SiFive, Krste Asanovic, is commercializing its version. . He said: "For small groups, RISC-V is quite simple to implement, which makes it possible to open many different RISC-V cores. So the diversity in the market is even greater. Processor Design Engineering Team You can find a version that meets their needs from multiple vendors (even open source), or they can make a design of their own. Freedom is the biggest feature here."
Asanovic believes that RISC-V can balance the competitive environment and allow vendors to compete in quality or customized implementations.
Using RISC-V Challenge
However, any new technology faces challenges. One obstacle for RISC-V is to use it as a single standard and maintain ISA consistency.
"If you split RISC-V, there will be many different RISC-V ISAs that are completely incompatible, so the foundation's goal is to ensure that there is a standard. Most core vendors understand that the biggest advantage of RISC-V is that it is generic. The software stack, whose development costs far exceed any core development costs, is of great interest to other core providers who do not need to maintain compilers, connectors, operating systems, and everything else. It was done by the community."
However, it takes time to reach maturity and trust.
Sonics's Wingard said: “If you are using one of the mainstream instruction set architectures today, you can choose no more than five debug environments. You can put anything else in this support community and from the vendor. With multiple options, these suppliers have a long history and good business model.The RISC-V world will have to re-create all of this, or figure out how to apply it to the current chip design for the ARM ecosystem. The main ecosystem, or find a way to adapt it to the current mainstream chip design ecosystem, the ARM ecosystem. RISC-V five-core commercial vendors must make their own decisions in this regard, this pair of RISC-V projects This is a huge obstacle."
Another obstacle to the adoption of RISC-V is the optimization of the implementation technology.
Wingard said: "They have the core of the job. They have already demonstrated this, but are they going to benchmark and prove that it is more efficient than the 7th generation core implementation of the commercial instruction set architecture? Maybe not for the time being. In the application There are times when there are a lot of issues that need to be addressed.We have an important job that needs to be done.We can come up with the idea that in a lot of SoCs, the CPU should be called the control processing unit, not the central processing unit, and this The actual throughput of the control processor may not matter, but for those who design these chips, they will never be sure.This is like the design margin they would rather have. For a given processing frequency, they would rather Get a higher performance machine."
Moreover, since the RISC-V instruction set can be extended by the user, some of these changes will affect the interaction of the core with the rest of the chip. He explained: "There are several classes here. One is to add new types of transactions that can appear on the NoC, or to increase the ability to directly talk directly to some closely coupled accelerator, such as ARM's DynamiQ technology. They have the ability to connect directly to AI coprocessors."
Asanovic admits that dealing with this division is a challenge. However, this foundation was established to manage this standard and let everyone agree. Companies that want to use RISC-V trademarks must pass compatibility tests first.
He said: "Another challenge is to deal with patent issues. We are very careful in the design of the basic ISA. This is very simple. We like to call it "boring RISC", so we return to the original RISC principle. Dave Patterson and ( The undergraduates at the University of California, Berkeley, together conducted a genealogical search and basically demonstrated the genealogy of all the instructions. For the basic ISA, they traced it back to RISC I, RISC II, RISC III, RISC IV."
In the membership agreement, the members agreed not to sue each other according to the basic ISA specifications. If they insist on doing so, they will lose their rights. Asanovic pointed out: "But if you examine other proprietary ISAs in terms of patent challenges, then you don't have much protection. You will see Company A sue Company B for using Company C's IP. Just as we recently saw It's the same as the graphics engine, so even if you buy from X, some companies will support it. And that's the same for RISC-V. The company is providing the core and providing protection in a standard business environment."
Although not mature, but growing up
The RISC-V instruction set architecture is not yet mature. "RISC-V is still in the early stages of development," Asanovic said. "For RISC-V, not everything has been built and actually existed, but the field is being taken at an incredible pace. Fill in. The open source community is more open to RISC-V, so the best and smartest way is to volunteer to help us push forward related issues."
Most of the projects that use RISC-V belong to the microcontroller class. For Unix-class application processors, the instruction set will take longer to move to the application. The goal of the Foundation this year is to establish a standard Unix platform, so it is necessary for the engineering team to understand what is required for the standard Unix version.
Asanovic said: "For developers, a major milestone in the development of this field is the release of the first Unix development board so that they can start porting Unix. For the RISC-V instruction set architecture, applications that can be considered for insertion are actually low End- and high-end, new applications such as machine learning accelerators, network processing or storage controllers, and even supercomputers. In these areas, people can try new ISAs."
If you want to build your own chips, your scope of work in the existing field is actually very limited, so doing your own thing in the high-end market while having a good software port is why people are interested in high-end products. If you are one of the large cloud service providers, then you definitely want to be your own processor chip. The RISC-V instruction set architecture may be something that you are very interested in. It may even be used heavily in three to four years.
Impact on the design process
In fact, from a microarchitecture point of view, RISC-V can have a large impact on the design process.
"If you give up using the existing IP core ecosystem because you are using different interfaces, you may encounter some major disruptions. But there is no impact on the integration, wiring, etc." Wingard said.
“When we started to build the infrastructure needed for chip upgrades, such as debugging infrastructure, RISC-V had a major impact. This is where the open-source RISC-V community must invest a lot of energy, and only then can It has become a technology that is comparable to existing rich technologies. At the software level, there is a lot of work to do around databases and device drivers. There is a lot of work at these stages of the design process."
Regarding the impact on the design process, Mohandass only focuses on one issue in the short term. "Assume that you have a new ISA and a new processor. You must thoroughly verify its performance in the short term. When it runs in real time, people are more concerned with robust performance. Are you concerned about the reliability of the architecture? Is it working? Once it is in silicon, When you get it in real time in production, these problems disappear. Only then can you see the real benefits of an elegant and simple architecture."
"Although RISC-V is not the first open source ISA, it has been in the integrated semiconductor industry for the past few years. The arrival of open source RISC-V is very interesting," said Ravi Thummarukudy, CEO of Mobivil.
"As the industry matures, companies are mainly achieving business growth through consolidation. Smaller companies find it difficult to replace the existing giants in most market segments, not to mention the maturity of the development. With the semiconductor manufacturing costs The increase in investment in small start-ups, especially in new CPU architectures, has decreased. The only real possibility of breakthrough innovation in CPU architecture is to create an open source environment through convergence aggregates and available funds."
At the same time, cloud computing and the Internet of Things are also driving semiconductor "consumption."
"In terms of data centers, Intel's ISA dominates the processor market, and ARM and other architectures have a very small market share," Thummarukudy said. "I don't expect much change in this situation. However, in terms of terminals or sensors, things This is totally different. This is the biggest innovation on the market today. The processor architecture of IoT devices requires low power consumption and cost-effective CPUs. This demand provides start-ups with an innovative way to innovate on smaller budgets. Various new SoCs. This is also the biggest advantage of RISC-V."
At the same time, Thummarukudy added that in such a software-driven world, software support for the RISC-V ISA is crucial. The success of ISA will depend on how fast a stable software ecosystem is created and maintained so that many new applications related to RISC-V can be enabled in the short term.
Graham Bell, vice president of marketing at Uniquify, believes that the RISC-V instruction set architecture will drive a new wave of the IoT space, especially when it requires scalable features (such as memory compilers) that are seen in semiconductor design IP, and will Introduced into processor development without proprietary barriers.
"RISC-V supports instruction set definition for problem solving, saves silicon and related costs, and allows proper balancing of low power consumption and processing performance requirements. It can create functional silicon for projects that spend between $1 and $200,000. This means that for those who are planning to start prototype projects, the threshold has been significantly reduced, and we can even see the funding of entrepreneurial crowdfunded projects outside the traditional design field.In addition to reducing entry costs, RISC-V The royalties (patent fees) for proprietary CPU IPs can be eliminated, and the production costs continue to decrease, which in turn drives more products to market faster.
Microsemi's Speers said that Linux support has been hit by landmark "collisions." Based on this, the RISC-V Foundation believes that Linux 4.1 is the time to provide support for RISC-V.
Another consideration in the software front-end is the possibility of using hardware switches to convert software methods.
“If I were a senior engineering manager, or a director of engineering, or a vice president of engineering, I would use the RISC-V instruction set architecture to begin the transition of my software approach. You already have a transition process, there is also a switch, because of people You will have to use the new debugger or other tools to debug RISC-V, you have a converter, you have a switch, because people will have to use the new debugger or other tools for RISC-V, so the method is also small Small changes," said Larry Lapides, vice president of sales for Imperas.
However, from a business model perspective, RISC-V is destructive, Mohandass said. "This is a completely open source approach that seeks to undermine ARM's influence and weaken the CPU or other cores such as work and their importance.
Wingard believes that if RISC-V succeeds, it will be more like a Linux model, and secondly, it will be like any other open source business model, because usually there are only a few companies behind most open source projects.
If you want to use open source code in a business environment, it is not uncommon for a user group that contributes the most to the open source project to form a service company, which makes people comfortable in the business environment. But in the Linux world, the competition around this role (service company) is fierce.
First of all, no company is the biggest contributor to the Linux kernel.
Second, the total number of lines of code is very large.
Third, if you don't have some kind of database and applications, and building blocks and coded things, the operating system itself is not very interesting, so there are many, many things to consider.
There are already many related organizations, of which Red Hat is the largest, but they are by no means the only ones. People are very excited about the different variants of Linux. They use different business model payment methods, but in reality most of the non-desktop computing now runs on Linux, and most of these machines are used for commercial purposes. We can see from here that software service companies need to pay fees, and they have reached a level of ubiquity that proves that this service-based model and corporate authorization model are effective.
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