The book "AXI4-based Programmable SOC System Design" is based on the "Principles and Applications of On-Chip Programmable Systems" textbook. It is an advanced tutorial on implementing embedded system applications based on the AXI4 specification and the Xilinx soft-core processor MicroBlaze. FPGAs are now being used more and more widely in various fields. Xilinx embeds the dedicated embedded processor PowerPC hard core, ARM Cortex-A9 MP hard core and embedded processor MicroBlaze soft core into the FPGA chip. This FPGA chip with integrated embedded processor is defined as an FPGA platform.
This FPGA-based embedded platform provides a flexible solution. In this solution, a large number of different IP soft cores and hard core resources are available on a single FPGA chip. These firmware and hardware can be upgraded at any time. This programmable structural feature greatly shortens the development time of the system, and the same platform can be applied in many fields, which improves the resource reuse rate of the platform. The system-on-chip based on Microblaze soft core processor is an important application of FPGA in the field of embedded systems. Due to its open design structure and design platform, designers can better understand and master the design principle and design of on-chip programmable system. Method and design process. In addition, the AXI4 specification is the next-generation SOC interconnection standard jointly developed by ARM, the world's leading embedded processor IP core provider, and Xilinx, a world-renowned programmable logic device provider. The development of this standard will be the development of future system-on-chip. Have a profound impact.
All the information in this book comes from Xilinx's technical manuals, literature and typical application cases, which fully reflect the latest technology and application results of Xilinx's on-chip programmable system, which can help readers master this latest technology as soon as possible. This book combines the basic principles of on-chip programmable systems with typical applications, making it easy for readers to understand and self-learn. This book is used as a teaching reference book for undergraduate and postgraduate students in information majors. It can also be used as a reference book for engineers and technicians engaged in on-chip programmable system design.
Section 1: Overview of AXI4 Xilinx works closely with ARM to define the AXI4 specification for high-performance FPGA-based systems and designs. And the Advanced eXtensible Interface (AXI) protocol is adopted on its next-generation programmable gate array chip.
The AXI bus is part of the Advanced Microcontroller Bus Architecture (AMBA). The first version of the AXI bus was included in AMBA 3.0 (released in 2003), and the second version of the AXI bus, AXI4, was included in AMBA 4.0 (released in 2010).
The goals of the latest generation of AMBA interfaces are:
Suitable for high bandwidth and low latency designs;
Allows higher frequency operation without the use of complex bridging methods;
Meet the component interface requirements under common conditions;
Memory controller for high initial access latency;
Provides flexibility for the implementation of the interconnect structure;
It is backward compatible with existing AHB and APB interfaces.
The key features of the AXI protocol are reflected in the following aspects:
Separate address/control and data phases;
Use byte gating to support unaligned data transfers;
Only the burst transaction of the starting address;
Independent read and write data channels enable low-cost direct memory access to DMA transfers;
Can issue multiple unresolved addresses;
Complete the disorderly transaction;
It is easy to add a register slice to meet the timing closure requirements;
The AXI protocol offers the following advantages over other protocols:
1. Provides higher productivity, mainly in the following aspects:
Integrate many different interfaces into one interface (AXI4), so users only need to know the interface of a single series;
Simplifies the integration of IP in different areas and makes the development of its own or third-party partner IP easier;
Design work is further simplified because AXI4 IP has been optimized for maximum performance, maximum throughput, and minimum latency;
2. Provides greater flexibility, mainly in the following areas:
Support embedded, DSP and logic version users;
Adjust the interconnection mechanism to meet system requirements: performance, area and power consumption;
Help designers build the most appealing products in the target market;
3. Provides a wide range of IP availability Third-party IP and EDA vendors generally adopt the open AXI4 standard, making the interface more widely available.
The AXI4-based target design platform accelerates embedded processing, DSP, and connectivity design development.
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