FIFO is very important, and the written tests of the logic design of various electronic companies that participated in the past will almost always be tested.
FIFO is the abbreviation of English First In First Out. It is a FIFO data buffer. The difference between it and ordinary memory is that there is no external read/write address line. This is very simple to use, but the disadvantage is that data can only be written sequentially. The sequential read data, whose data address is automatically incremented by the internal read/write pointer, cannot be read or written to a specified address by the address line like a normal memory.
FIFO generally used for data transmission between different clock domains, such that an end of the FIFO AD data acquisition, and the other end is a PCI bus computer, it is assumed that the AD collection rate 16 100K SPS, then the amount of data per second 100K & TImes; 16bit = 1.6Mbps, while the PCI bus speed is 33MHz, the bus width is 32bit, and its maximum transmission rate is 1056Mbps. FIFO can be used as data buffer between two different clock domains. In addition, for different width data interfaces, FIFO can also be used, for example, 8-bit data output of single-chip microcomputer, and DSP may be 16-bit data input. When the single-chip microcomputer is connected with DSP, FIFO can be used to achieve data matching.
The classification of the FIFO is the clock domain in which the FIFO operates, and the FIFO can be divided into a synchronous FIFO and an asynchronous FIFO. The synchronous FIFO means that the read clock and the write clock are the same clock. Read and write operations occur simultaneously on the clock edge. Asynchronous FIFO means that the read and write clocks are inconsistent and the read and write clocks are independent of each other.
Difficulties in FIFO Design The difficulty in FIFO design is how to determine the empty/full state of the FIFO. In order to ensure that the data is correctly written or read without a benefit or readout condition, it must be ensured that the FIFO is not full when it is full. Reading operations cannot be performed in an empty state. How to judge the full/empty of the FIFO becomes the core problem of the FIFO design.
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One of the Verilog codes of the synchronous FIFO
Verified in modlesim.
/************************************************* *****A fifo controller verilog descripTIon.*************************************** *************** / module fifo (datain, rd, wr, rst, clk, dataout, full, empty); input [7: 0] datain; input rd, wr, rst , clk; output [7: 0] dataout; output full, empty; wire [7: 0] dataout; reg full_in, empty_in; reg [7: 0] mem [15: 0]; reg [3: 0] rp, Wp;assign full = full_in;assign empty = empty_in;// memory read outassign dataout = mem[rp];// memory write inalways@(posedge clk) begin if(wr && ~full_in) mem[wp]<=datain; End// memory write pointer incrementalways@(posedge clk or negedge rst) begin if(!rst) wp<=0; else begin if(wr && ~full_in) wp<= wp+1'b1; endend// memory read pointer Incrementalways@(posedge clk or negedge rst) begin if(!rst) rp <= 0; else begin if(rd && ~empty_in) rp <= rp + 1'b1; endend// Full signal generatealways@(posedge clk or negedge Rst) begin if(!rst) full_in <= 1'b0; else begin if( (~rd && wr)&&((wp==rp-1)||(rp==4'h0&&& Wp==4'hf))) full_in <= 1'b1; else if(full_in && rd) full_in <= 1'b0; endend// Empty signal generatealways@(posedge clk or negedge rst) begin if(!rst) Empty_in <= 1'b1; else begin if((rd&&~~)&&(rp==wp-1 || (rp==4'hf&&wp==4'h0))) empty_in<=1'b1; else if (empty_in && wr) empty_in<=1'b0; endendendmodule
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Verilog code of the synchronous FIFO
This design of FIFO is based on triggers. Width, depth expansion is more convenient, structured and strong. The following code has been verified in modelsim.
Module fifo_cell (sys_clk, sys_rst_n, read_fifo, write_fifo, fifo_input_data, next_cell_data, next_cell_full, last_cell_full, cell_data_out, cell_full); parameter WIDTH =8; parameter D = 2; input sys_clk; input sys_rst_n; input read_fifo, write_fifo; input [WIDTH-1 :0] fifo_input_data; input [WIDTH-1:0] next_cell_data; input next_cell_full, last_cell_full; output [WIDTH-1:0] cell_data_out; output cell_full; reg [WIDTH-1:0] cell_data_reg_array; reg [WIDTH-1:0 ] cell_data_ld; reg cell_data_ld_en; reg cell_full; reg cell_full_next; assign cell_data_out = cell_data_reg_array; always @ (posedge sys_clk or n Egedge sys_rst_n) if (!sys_rst_n) cell_full <= #D 0; else if (read_fifo || write_fifo) cell_full <= #D cell_full_next; always @(write_fifo or read_fifo or next_cell_full or last_cell_full or cell_full) casex ({read_fifo, write_fifo} 2'b00: cell_full_next = cell_full; 2'b01: cell_full_next = next_cell_full; 2'b10: cell_full_next = last_cell_full; 2'b11: cell_full_next = cell_full; endcase always @(posedge sys_clk or negedge sys_rst_n) if (!sys_rst_n) cell_data_reg_array [ WIDTH-1:0] <= #D 0; else if (cell_data_ld_en) cell_data_reg_array [WIDTH-1:0] <= #D cell_ Data_ld [WIDTH-1:0]; always @(write_fifo or read_fifo or cell_full or last_cell_full) casex ({write_fifo,read_fifo,cell_full,last_cell_full}) 4'bx1_xx: cell_data_ld_en = 1'b1; 4'b10_01: cell_data_ld_en = 1' B1; default: cell_data_ld_en =1'b0; endcase always @(write_fifo or read_fifo or next_cell_full or cell_full or last_cell_full or fifo_input_data or next_cell_data) casex ({write_fifo, read_fifo, next_cell_full, cell_full, last_cell_full}) 5'b10_x01: cell_data_ld[WIDTH- 1:0] = fifo_input_data[WIDTH-1:0]; 5'b11_01x: cell_data_ld[WIDTH-1:0] = fifo_input_data[WIDTH-1:0]; default: cell_data_ld[WIDTH-1:0] = next_cell_data[WIDTH -1:0]; endcaseendmod Ule
Module fifo_4cell(sys_clk, sys_rst_n, fifo_input_data, write_fifo, fifo_out_data, read_fifo, full_cell0, full_cell1, full_cell2, full_cell3); parameter WIDTH = 8; parameter D = 2; input sys_clk; input sys_rst_n; input [WIDTH-1:0] fifo_input_data; Output [WIDTH-1:0] fifo_out_data; input read_fifo, write_fifo; output full_cell0, full_cell1, full_cell2, full_cell3; wire [WIDTH-1:0] dara_out_cell0, data_out_cell1, data_out_cell2, data_out_cell3, data_out_cell4; wire full_cell4; fifo_cell #(WIDTH, D) cell0 ( .sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .fifo_input_data (fifo_input_data[WIDTH-1:0]), .write_fifo (write_fifo), .next_cell_data (data_out_cell1[WIDTH-1:0]), .next_cell_full (full_cell1), .last_cell_full (1'b1), .cell_data_out (fifo_out_data [WIDTH-1:0]), .read_fifo (read_fifo), .cell_full (full_cell0) );
fifo_cell # (WIDTH, D) cell1 (.sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .fifo_input_data (fifo_input_data [WIDTH-1: 0]), .write_fifo (write_fifo), .next_cell_data (data_out_cell2 [WIDTH-1: 0 ]), .next_cell_full (full_cell2), .last_cell_full (full_cell0), .cell_data_out (data_out_cell1 [WIDTH-1: 0]), .read_fifo (read_fifo), .cell_full (full_cell1)); fifo_cell # (WIDTH, D) cell2 ( .sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .fifo_input_data (fifo_input_data[WIDTH-1:0]), .write_fifo (write_fifo), .next_cell_data (data_out_cell3[WIDTH-1:0]), .next_cell_full (full_cell3), .last_cell_full (full_cell1), .cell_data_out (data_out_cell2[W IDTH-1:0]), .read_fifo (read_fifo), .cell_full (full_cell2) );
fifo_cell # (WIDTH, D) cell3 (.sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .fifo_input_data (fifo_input_data [WIDTH-1: 0]), .write_fifo (write_fifo), .next_cell_data (data_out_cell4 [WIDTH-1: 0 ]), .next_cell_full (full_cell4), .last_cell_full (full_cell2), .cell_data_out (data_out_cell3[WIDTH-1:0]), .read_fifo (read_fifo), .cell_full (full_cell3) ); assign data_out_cell4[WIDTH-1:0] = {WIDTH{1'B0}}; assign full_cell4 = 1'b0;endmodule
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One of the asynchronous FIFO Verilog code
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