Researchers at Stanford University have demonstrated that field effect transistors made from a single layer of molybdenum disulfide (MoS2) can successfully drive resistive random access memories. The results reported at the IEEE International Electronic Equipment Conference recently represent a key milestone in the integration of memory and logic in a single 3D integrated chip.
The chip developed by Stanford researchers is called the "single transistor single-impedance memory" (1T1R) unit. Such a 1T1R memory cell can provide significant benefits over a memory cell that includes a resistive memory but no transistors.
Without a transistor, all of the memory cells in the resistive memory chip are connected to different lines, making the memory array a large resistor network. When a memory cell is selected to read its contents, the current comes not only from the selected memory cell, but also from the leakage current of all unselected memory cells in the memory array. Due to these leakage currents, the voltage on the selected memory cell will be less than the applied voltage.
The advantage of the 1T1R memory cell is that it can isolate the target memory cell from other memory cells by turning the transistor on and off, thereby suppressing leakage current. “Although silicon field effect transistors can also be used in 1T1R memory cells, the advantage of single-layer molybdenum disulfide is that the transfer process can be performed at lower temperatures, thus facilitating mutual implementation of the memory and logic layers in a single chip. Three-dimensional stacking configuration," said Rui Yang, a postdoctoral researcher at Stanford University. He is the lead author of H.-S internal research, and Philip Wong is at the Nanoelectronics lab.
Yang added that "the current channel of molybdenum disulfide FETs is only atomic, and the nano-level vias can be used as channels for connecting different layers of the chip. This allows more parts of the chip to access the memory more efficiently."
In normal operation, the resistive memory stores data as a resistor value. For a resistive memory using a 1T1R memory cell, when the field effect transistor in the memory cell (in this case, a molybdenum disulfide-based field effect transistor) is turned on, the memory cell is in the write mode. At this point, the transistors of other unselected cells will be off and the voltage will be applied to the top electrode of the selected resistive memory and the source electrode of the molybdenum disulfide transistor.
The transistor is connected in series with the resistive memory. When the resistive memory transitions from the high resistance state to the low resistance state, the top electrode of the resistive memory is in a high state, and the source electrode of the field effect transistor is grounded. The transistor drive current passes through the resistive memory and controls the current, and when the voltage changes periodically, the resistance value is further regulated. Currently, the production of resistive memory can be implemented using CMOS compatible materials.
However, it is said that the industry is not yet ready to manufacture two-dimensional materials to the same extent. "We need to find a reliable way to grow and transfer 2D materials on a wafer and integrate 2D transistors with resistive memory on a monolithic 3D stack," he said.
In addition to growing and transferring two-dimensional materials on wafers, these devices still have many problems to overcome. Yang believes that they need to make the device smaller, make the 1T1R memory array larger, and further improve device uniformity. He believes that the technology is very promising. Molybdenum disulfide and resistive memory not only make it possible to scale out the scale of the in-plane circuit, but also provide the possibility of extending the circuit scale in the vertical direction by three-dimensional stacking. Yang added: "To achieve this goal, we plan to create multiple memory and logic layers in 3D circuits and have the ability to compute in memory."
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