Data transfer class instructions are the most frequently used types of instructions when programming. The mnemonic of the general data transfer class instruction is "MOV". The common format is as follows:
MOV <destination operand>, <source operand>
The data transfer class instruction transfers the source operand to the destination operand. After the instruction is executed, the source operand does not change and the destination operand is modified to the source operand. Therefore, the data transfer operation is a "copy" nature, not a "moving".
The data transfer class instruction does not affect the flag bits. The flag bits referred to here refer to Cy, Ac, and OV, but do not include the check accumulator parity flag bit P.
1. Instruction for the operand of the accumulator
The function of this set of instructions is to send the contents of the source operand to the accumulator A. The source operands have register addressing, direct addressing, indirect addressing, and immediate addressing, such as instructions:
2. Instruction for the purpose of Rn
The function of this group of instructions is to send the contents of the source operand to one of the RO to R7 registers in the current working register area.
3. Instruction with operand for direct address direct
The function of this set of instructions is to feed the source operand to the location specified by the direct address. Direct refers to the internal RAM or SFR address.
4. Instruction with a register indirect address as the destination operand
The function of this set of instructions is to feed the source operand content into the storage unit specified by RO or R1.
5. 16-bit transfer instruction
The function of this instruction is to send a 16-bit immediate value to the DPTR to set the address pointer of the data memory. There are two DPTRs in the AT89S51 , which are selected by setting the DPS bit in the special function register AUXR1. When DPS-I, the DPTR in the instruction is DPTR1, DPTRO is masked, and vice versa. DPTR is a 16-bit data pointer, and can be divided into two 8-bit registers, DPH and DPL. It is very flexible and convenient. With two DPTRs, frequent stack operations can be avoided.
For all MOV class instructions, accumulator A is a particularly important 8-bit register that the CPU has for operation instructions that are not available in other registers. The addition, subtraction, multiplication, and division instructions to be described later all use A as the destination operand. Rn is RO to R7 in the register group currently selected by the CPU. The memory location specified by the direct address is OOH to 7FH of the internal RAM and the special function register (address range is 80H to FFH). In the indirect address, RO or Rl is used as the address pointer of the internal RAM, and 128 units of OOH to 7FH of the internal RAM can be accessed.
6. Stack operation instruction
In the internal RAM of the AT89S51, a LIFO (Last In First Out) area can be set, which is called a stack. There is a stack pointer SP in the special function register that specifies the stack top position of the stack. There are two types of stack operations: push and pop. Therefore, there are two stack operation instructions in the instruction system.
(1) Push instruction
The function of this instruction is to first increment the stack pointer SP and then send the contents of the direct to the internal RAM unit indicated by the stack pointer SP.
For example, when (SP)=60H, (A)=30H, (B)=70H, execute the following command
The result was (61H) = 30H, (62H) = 70H, and (SP) = 62H.
(2) pop instruction
The function of this instruction is to send the contents of the top of the stack (internal RAM unit) indicated by the stack pointer SP into the direct byte unit, and the stack pointer SP is decremented by one.
For example, when (SP) = 62H, (62H) = 70H, (61H) = 30H, execute the following command:
The result was (DPTR) = 7030H, (SP) = 60H.
7. Accumulator A and external data memory RAM/IO transfer instructions
The mnemonic of the above four instructions is "X" after the MOV. The "X" indicates that the AT89S51 MCU accesses the off-chip RAM memory or I/O port, and reads a word in the external RAM memory or I/O port. The data of the section is added to the accumulator A, or one byte of data in the accumulator A is written into the external RAM memory or the I/O port. Therefore, RD (reverse) (P3.7) is valid when the first two instructions are executed; WR (P3.6) is valid when the two instructions are executed.
The 16-bit DPTR is used for indirect addressing to address the entire 64KB off-chip data memory space. The upper 8-bit address (DPH) is output by the P2 port, and the lower 8-bit address (DPL) is output by the PO port.
Indirect addressing with Ri(i=0.1) addresses the off-chip 256-cell data memory. The 8-bit address is output by the PO port, latched in the address latch, and then the PO port acts as an 8-bit data port.
8. Table lookup instruction
There are two such instructions, all of which are single-byte instructions. This is the only two instructions in the AT89S51 instruction system that read the table data in the program memory. Since the program memory can only be read and cannot be written, its data transfer is unidirectional, that is, the data is read from the program memory to the accumulator. Both table lookup instructions use the base register plus the index register indirect addressing mode.
This instruction uses the PC as the base register. The contents of A are added as the unsigned integer and the current value of the PC (the start address of the next instruction) to obtain a new 16-bit address. The program memory location specified by the address is specified. The contents are sent to accumulator A.
For example: when (A)=30H, execute the instruction at address 1000H.
This instruction occupies one byte. The address of the next instruction is 1001H, (PC)=1001H plus 30H in A, which is 1031H. The result is that the content of 1031H in the program memory is sent to accumulator A.
The advantage of this instruction is that it does not change the state of the special function registers and the PC. The constants in the table can be retrieved according to the contents of A. The disadvantage is that the form can only be stored in the +256 units of the address of the table lookup instruction, the size of the table is limited, and the form can only be used by a program.
This instruction uses DPTR as the base register, and the contents of A are added as the unsigned number and the contents of the DPTR to obtain a 16-bit address, and the contents of the program memory unit specified by the address are sent to the accumulator A.
For example: (DPTR) = 8100H, (A) = 40H, execute the command
The result is that the 8140H unit contents in the program memory are sent to the accumulator A.
The execution result of this table lookup instruction is only related to the contents of the pointer DPTR and the accumulator A, and is independent of the address stored in the instruction and the address stored in the constant table, so the size and position of the table can be arbitrarily arranged in the 64 KB program memory space. A table can be common to individual blocks.
The mnemonics of the above two instructions are all added "C" after the MOV, and "C" is the first letter of the CODE, which means the code in the program memory. When the above two instructions are executed, the PSEN pin signal (program memory read) of the microcontroller is valid.
9. Byte swap instruction
The function of this set of instructions is to exchange the contents of accumulator A and the contents of the source operands. Source operands have register addressing, direct addressing, and register indirect addressing. E.g:
Execute the following instructions:
The result was (A) = OFH, (R7) = 80H, (40H) = 08H, and (30H) = FOH.
10. Nibble swap instruction
The function of this instruction is that the lower 4 bits of the accumulator are swapped with the lower 4 bits of the internal RAM. For example: (RO) = 60H, (60H) = 3EH, (A) = 59H, after executing the "XCHD A, @RO" command, then (A) = 5EH, (60H) = 39H.
MOV <destination operand>, <source operand>
The data transfer class instruction transfers the source operand to the destination operand. After the instruction is executed, the source operand does not change and the destination operand is modified to the source operand. Therefore, the data transfer operation is a "copy" nature, not a "moving".
The data transfer class instruction does not affect the flag bits. The flag bits referred to here refer to Cy, Ac, and OV, but do not include the check accumulator parity flag bit P.
1. Instruction for the operand of the accumulator
The function of this set of instructions is to send the contents of the source operand to the accumulator A. The source operands have register addressing, direct addressing, indirect addressing, and immediate addressing, such as instructions:
2. Instruction for the purpose of Rn
The function of this group of instructions is to send the contents of the source operand to one of the RO to R7 registers in the current working register area.
3. Instruction with operand for direct address direct
The function of this set of instructions is to feed the source operand to the location specified by the direct address. Direct refers to the internal RAM or SFR address.
4. Instruction with a register indirect address as the destination operand
The function of this set of instructions is to feed the source operand content into the storage unit specified by RO or R1.
5. 16-bit transfer instruction
The function of this instruction is to send a 16-bit immediate value to the DPTR to set the address pointer of the data memory. There are two DPTRs in the AT89S51 , which are selected by setting the DPS bit in the special function register AUXR1. When DPS-I, the DPTR in the instruction is DPTR1, DPTRO is masked, and vice versa. DPTR is a 16-bit data pointer, and can be divided into two 8-bit registers, DPH and DPL. It is very flexible and convenient. With two DPTRs, frequent stack operations can be avoided.
For all MOV class instructions, accumulator A is a particularly important 8-bit register that the CPU has for operation instructions that are not available in other registers. The addition, subtraction, multiplication, and division instructions to be described later all use A as the destination operand. Rn is RO to R7 in the register group currently selected by the CPU. The memory location specified by the direct address is OOH to 7FH of the internal RAM and the special function register (address range is 80H to FFH). In the indirect address, RO or Rl is used as the address pointer of the internal RAM, and 128 units of OOH to 7FH of the internal RAM can be accessed.
6. Stack operation instruction
In the internal RAM of the AT89S51, a LIFO (Last In First Out) area can be set, which is called a stack. There is a stack pointer SP in the special function register that specifies the stack top position of the stack. There are two types of stack operations: push and pop. Therefore, there are two stack operation instructions in the instruction system.
(1) Push instruction
The function of this instruction is to first increment the stack pointer SP and then send the contents of the direct to the internal RAM unit indicated by the stack pointer SP.
For example, when (SP)=60H, (A)=30H, (B)=70H, execute the following command
The result was (61H) = 30H, (62H) = 70H, and (SP) = 62H.
(2) pop instruction
The function of this instruction is to send the contents of the top of the stack (internal RAM unit) indicated by the stack pointer SP into the direct byte unit, and the stack pointer SP is decremented by one.
For example, when (SP) = 62H, (62H) = 70H, (61H) = 30H, execute the following command:
The result was (DPTR) = 7030H, (SP) = 60H.
7. Accumulator A and external data memory RAM/IO transfer instructions
The mnemonic of the above four instructions is "X" after the MOV. The "X" indicates that the AT89S51 MCU accesses the off-chip RAM memory or I/O port, and reads a word in the external RAM memory or I/O port. The data of the section is added to the accumulator A, or one byte of data in the accumulator A is written into the external RAM memory or the I/O port. Therefore, RD (reverse) (P3.7) is valid when the first two instructions are executed; WR (P3.6) is valid when the two instructions are executed.
The 16-bit DPTR is used for indirect addressing to address the entire 64KB off-chip data memory space. The upper 8-bit address (DPH) is output by the P2 port, and the lower 8-bit address (DPL) is output by the PO port.
Indirect addressing with Ri(i=0.1) addresses the off-chip 256-cell data memory. The 8-bit address is output by the PO port, latched in the address latch, and then the PO port acts as an 8-bit data port.
8. Table lookup instruction
There are two such instructions, all of which are single-byte instructions. This is the only two instructions in the AT89S51 instruction system that read the table data in the program memory. Since the program memory can only be read and cannot be written, its data transfer is unidirectional, that is, the data is read from the program memory to the accumulator. Both table lookup instructions use the base register plus the index register indirect addressing mode.
This instruction uses the PC as the base register. The contents of A are added as the unsigned integer and the current value of the PC (the start address of the next instruction) to obtain a new 16-bit address. The program memory location specified by the address is specified. The contents are sent to accumulator A.
For example: when (A)=30H, execute the instruction at address 1000H.
This instruction occupies one byte. The address of the next instruction is 1001H, (PC)=1001H plus 30H in A, which is 1031H. The result is that the content of 1031H in the program memory is sent to accumulator A.
The advantage of this instruction is that it does not change the state of the special function registers and the PC. The constants in the table can be retrieved according to the contents of A. The disadvantage is that the form can only be stored in the +256 units of the address of the table lookup instruction, the size of the table is limited, and the form can only be used by a program.
This instruction uses DPTR as the base register, and the contents of A are added as the unsigned number and the contents of the DPTR to obtain a 16-bit address, and the contents of the program memory unit specified by the address are sent to the accumulator A.
For example: (DPTR) = 8100H, (A) = 40H, execute the command
The result is that the 8140H unit contents in the program memory are sent to the accumulator A.
The execution result of this table lookup instruction is only related to the contents of the pointer DPTR and the accumulator A, and is independent of the address stored in the instruction and the address stored in the constant table, so the size and position of the table can be arbitrarily arranged in the 64 KB program memory space. A table can be common to individual blocks.
The mnemonics of the above two instructions are all added "C" after the MOV, and "C" is the first letter of the CODE, which means the code in the program memory. When the above two instructions are executed, the PSEN pin signal (program memory read) of the microcontroller is valid.
9. Byte swap instruction
The function of this set of instructions is to exchange the contents of accumulator A and the contents of the source operands. Source operands have register addressing, direct addressing, and register indirect addressing. E.g:
Execute the following instructions:
The result was (A) = OFH, (R7) = 80H, (40H) = 08H, and (30H) = FOH.
10. Nibble swap instruction
The function of this instruction is that the lower 4 bits of the accumulator are swapped with the lower 4 bits of the internal RAM. For example: (RO) = 60H, (60H) = 3EH, (A) = 59H, after executing the "XCHD A, @RO" command, then (A) = 5EH, (60H) = 39H.
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